1. Field of the Invention
The present invention relates to a semiconductor memory device and a driving method of the same, and particularly, to a construction of a circuit generating a word line drive signal to be transmitted to a selected word line.
2. Description of the Background Art
FIG. 1 schematically shows an overall construction of a dynamic semiconductor memory device in the prior art. In FIG. 1, the dynamic semiconductor memory device 500 includes a memory cell array 501 having dynamic memory cells arranged in a matrix of rows and columns, an address buffer 502 which receives externally applied address signals A0-An and generates internal address signals, a row address decoder 503 which decodes the internal row address signals supplied from address buffer 502 and selects a corresponding row in memory cell array 501, and a word driver 504 which is responsive to an output of row address decoder 503 to raise the potential of the word line disposed in the selected row.
Word river 504 transmits a word line drive signal, which is supplied from a word line drive signal generating circuit 505, to the word line corresponding to the row selected by row address decoder 503.
Semiconductor memory device 500 further includes a column address decoder 506 which decodes an internal column address signal supplied from address buffer 502 and selects a corresponding column in memory cell array 501, a sense amplifier which detects and amplifies data of memory cells in the selected row in memory cell array 501, and an IO gate which connects the column selected by column address decoder 506 to an I/O circuit 508. In FIG. 1, the sense amplifier and the I0 gate are represented by one block 507.
Semiconductor memory device 500 further includes a clock buffer 509 which generates an internal control signal in response to externally applied control signals *RAS (row address strobe signal), *CAS (column address strobe signal) and *WE (write enable signal), and a word line drive signal generating circuit 505 which generates the word line drive signal in response to an internal row address strobe signal /RAS supplied from clock buffer 509. Word line drive signal generating circuit 505 includes an RX generating circuit 511 which is responsive to an internal row address strobe signal /RAS to generate a word line drive signal RX at a power supply level, and a boosting circuit 522 which boosts up a signal generated by RX generating circuit 511. Drive signal boosted by boosting circuit 522 is transferred through word driver 504 to the selected word line (selected row).
In the data write operation, I/O circuit 508 produces internal write data from external write data D/Q, and transfers the same to block 507. In the data read operation, I/O circuit 508 produces external read data D/Q in accordance with the internal read data read through block 507. I/O circuit 508 may have a construction, in which input buffer for writing the data and an output buffer for reading the data are independent from each other, and are connected to different pin terminals, respectively. These input buffer and output buffer may be connected to the same pin terminal.
Address buffer 502 is responsive to internal control signal (/RAS and /CAS) supplied from clock buffer 509 to generate the internal row address signal and the internal column address signal. Row address decoder 503 and column address decoder 506 are responsive to internal control signals /RAS and /CAS, respectively, to decode the internal address signals applied thereto. Address buffer 502 receives, as address signal A0-An, the row address signal and the column address signal in a time division multiplexing manner. Alternatively, address buffer 502 may simultaneously receives the row address signal and the column address signal, and clock buffer 509 may receive a chip selecting signal *CS, which determines a timing of strobing an address signal of address buffer 502.
I/O circuit 508 is responsive to an internal write control signal/WE supplied from clock buffer 509 to produce the internal write data or external read data.
The semiconductor memory device further includes a sense amplifier drive circuit 510 which drives a sense amplifier included in block 507 in response to internal row address strobe signal/RAS. Sense amplifier drive circuit 510 is responsive to internal row address strobe signal /RAS to drive the sense amplifier included in sense amplifier/IO gate block 507.
FIG. 2 shows a specific construction of memory cell array 501 and sense amplifier/IO gate block 507 shown in FIG. 1. Memory cell array 501 includes a plurality of bit line pairs, each of which is connected to the memory cells on one column, and a plurality of word lines, each of which is connected to the memory cells on one row. FIG. 2 representatively shows a pair of bit lines BL and /BL and two word lines WL1 and WL2.
In FIG. 2, memory cell array 501 includes a memory cell MC1 disposed at the crossing of bit line BL and word line WL1, a memory cell MC2 disposed at the crossing of bit line /BL and word line WL2, and a precharging/equalizing circuit PE which is responsive to a precharging/equalizing signal .phi.PR to equalize and precharge potentials of bit lines BL and /BL to be a predetermined potential VBL.
Memory cell MC1 includes a capacitor C1 storing information and an n-channel MOS transistor (insulated gate type field effect transistor) NT4 which is responsive to the signal potential on word line WL1 to electrically connect capacitor C1 to bit line BL. Capacitor C1 has one electrode (storage node) connected to a drain of transistor NT4 and the other electrode (cell plate) connected to a predetermined potential VG.
Memory cell MC2 includes a capacitor C2 for storing information, and an n-channel MOS transistor NT5 which is responsive to the signal potential on word line WL2 to electrically connect capacitor C2 to bit line /BL.
Precharging/equalizing circuit PE includes an n-channel MOS transistor NT1 which is responsive to a precharging/equalizing signal .phi.PR to transfer predetermined precharge potential VBL to bit line BL, an n-channel MOS transistor NT3 which is responsive to precharging/equalizing signal .phi.PR to transfer precharge potential VBL to bit line /BL, and an n-channel MOS transistor NT2, which is responsive to precharging/equalizing signal .phi.PR to electrically connect bit line BL and bit line /BL.
Sense amplifier/IO gate block 507 includes a p-channel sense amplifier PSA which charges the potential of bit line BL or /BL having a higher potential to a high level of the operating power supply potential VCC level, an n-channel sense amplifier NSA which discharges the potential of bit line BL or /BL having a lower potential to the ground potential, and n-channel MOS transistors NT8 and NT9 which are responsive to a column selecting signal Yi from the column address decoder to connect bit lines BL and /BL to internal data lines DB and /DB. Transistors NT8 and NT9 provide an IO gate IOG.
P-channel sense amplifier PSA includes cross-coupled p-channel MOS transistors PT1 and PT2. Transistor PT1 has a drain connected to bit line BL and a gate of transistor PT2, a gate connected to bit line/BL and a drain of transistor PT2, and a source connected to a signal line 550. Transistor PT2 has the gate connected to the drain of transistor PT1 and bit line BL, the drain connected to the gate of transistor PT1 and bit line/BL, and a source connected to signal line 550.
N-channel sense amplifier NSA includes n-channel MOS transistors NT6 and NT7, of which gates and drains are cross-coupled. Transistor NT6 has the drain connected to bit line BL, a source connected to a signal line 551, and the gate connected to bit line /BL. Transistor NT7 has the gate connected to bit line BL, the drain connected to bit line /BL and a source connected to signal line 551.
Sense amplifier drive circuit 510 includes a sense amplifier activation signal generating circuit 522 which is responsive to internal row address strobe signal /RAS supplied from clock buffer 509 to produce sense amplifier activation signals /.phi.SP and .phi.SN, and a sense amplifier activating circuit 514 which is responsive to sense amplifier activation signals /.phi.SP and .phi.SN to activate sense amplifiers PSA and NSA. Sense amplifier activating circuit 514 includes a p-channel MOS transistor PT3 which is responsive to sense amplifier activation signal /.phi.SP to charge signal line 550 up to operating power supply potential VCC, and an n-channel MOS transistor NT10 which is responsive to sense amplifier activation signal .phi.SN to connect signal line 551 to the ground potential.
FIG. 3 shows a construction of circuitry for a word line drive. In FIG. 3, clock buffer 509 includes an RAS buffer 609 which receives an externally applied row address strobe signal *RAS and generates an internal row address strobe signal /RAS. RAS buffer 609 may generate an internal row address strobe signal RAS of positive logic. RX generating circuit 511 includes an inverter circuit 610 which inverts internal row address strobe signal /RAS, an n-channel MOS transistor NT20 which is responsive to an output of inverter circuit 610 to charge an output node NO to the operating power supply potential VCC level, a delay circuit 611 which delays internal row address strobe signal /RAS by a predetermined time, and an n-channel MOS transistor NT21 which is responsive to an output of delay circuit 611 to discharge output node NO to the ground potential. In place of inverter circuit 610 and n-channel MOS transistor NT2, an p-channel MOS transistor which receives internal row address strobe signal /RAS at its gate may be used.
Transistor NT20 has a current supply capability larger than that of transistor NT21. When the signal /RAS falls to the low level, i.e., active state, transistor NT20 becomes conductive, and thus output node NO is charged to supply voltage VCC level, i.e., high level. After a predetermined time period, n-channel MOS transistor NT21 is turned off. When signal /RAS rises to the high level, i.e., inactive state, transistor NT20 is turned off. At this time, the output of delay circuit 611 is still at the low level and transistor NT21 is in the off-state. In this condition, therefore, output node NO still maintains the high level. After a predetermined time period, the output of delay circuit 611 goes to the high level and transistor NT21 is turned on, so that output node NO is discharged to the ground potential level, i.e., low level, because transistor NT20 is off.
Boosting circuit 512 includes a delay circuit 612 which delays the output of RX generating circuit 511 by a predetermined time period, and a boosting capacitance 613 which is responsive to the output of delay circuit 612 to boost up the word line drive signal RX. Delay circuit 612 includes an even number of cascaded inverter circuits IV. Capacitor 613 further boosts up the high level potential of word line drive signal RX by its capacitance-coupling.
Row address decoder 503 includes row decoder circuits 603, each of which is disposed correspondingly to the word line. A row decoder circuit 603 is selected to generate a row selection signal at the high level when the applied internal address signals have a predetermined combination of logical values "0" and "1".
Word driver 504 includes drive circuits 604, each of which is disposed corresponding to the word line. Each drive circuit 604 includes an n-channel MOS transistor NT30 which is responsive to an output of row decoder circuit 603 to transfer word line drive signal RX to a corresponding word line WL, and an n-channel MOS transistor NT31 which is responsive to a reset signal (which is generally generated in response to internal row address strobe signal /RAS through a generating path (not shown)) to discharge the potential of word line WL to the ground potential. If word line drive signal RX is boosted up to or above the operating power supply potential, the gate potential of transistor NT30 is boosted up, due to the capacitance-coupling between the gate and drain and between the gate and source, to the level equal to or higher than the boosted level of the word line drive signal. Thereby, the boosted word line drive signal RX is transferred through transistor NT30 to word line WL. Then, an operation of the semiconductor memory device shown in FIGS. 1-3 will be briefly described below with reference to the operation waveform diagrams of FIGS. 4(a) to 4(f).
When external row address strobe signal *RAS falls to the low level, the semiconductor memory device enters the memory cycle. In response to the falling of signal *RAS, precharging/equalizing signal .phi.PR falls to the low level. The generating path for signal .phi.PR is not shown. Responsively, precharging/equalizing circuit PE is inactivated, and transistors NT1-NT3 are turned off. Bit lines BL and /BL are brought to the floating state at precharge potential VBL (generally at the level of VCC/2). Then, word line drive signal generating circuit 505 generates word line drive signal RX, which is further boosted up by boosting circuit 512 to the level equal to or above operating power supply voltage VCC level.
Meanwhile, address buffer 502 strobes and latches applied address signals A0-An to generate internal row address signals. Row address decoder 503 decodes the internal row address signals, whereby a row decoder circuit 603 and a drive circuit 504 are selected. Word line drive signal RX supplied from word line drive signal generating circuit 505 is transferred through drive circuit 504 to the corresponding word line WL.
When the potential of word line WL (assuming that word line WL1 is selected) rises, transistor NT4 of memory cell MC1 is turned on, and thus the charges accumulated in capacitor C1 are transferred to bit line BL. If memory cell MC1 has stored the information of "0", the potential of bit line BL lowers slightly below the precharge potential, as shown in FIG. 4(f). Bit line /BL maintains precharge potential VBL.
Then, sense amplifier activation signal generating circuit 510 generates sense amplifier activation signals .phi.SN and/.phi.SP to activate sense amplifier activating circuit 514, and thus sense amplifiers PSA and NSA operate.
Consequently, a slight potential difference generated between bit lines BL and /BL is amplified, so that the potential of bit line BL goes to the ground potential level and the potential of bit line /BL goes to operating power supply voltage VCC level.
Then, externally applied column address strobe signal *CAS goes to the active state, and address buffer 502 generates the internal column address signals, which are applied to column address decoder 506. Column address decoder 506 decodes the applied internal address signals to generate column selecting signal Yi which selects the corresponding column in memory cell array 501. Thereby, bit lines BL and /BL are connected through IO gate IOG to internal data lines DB and /DB, respectively.
In the data write operation, write instructing signal /WE is in the active state, i.e., at the low level. I/O circuit 508 transfers the internal write data to internal data lines DB and /DB, which are then transferred to corresponding bit lines BL and /BL and the data is written in memory cell MC1.
In the data read operation, the potentials of bit lines BL and /BL are transferred to internal data lines DB and /DB, and then are transferred to I/O circuit 508, by which external read data D/Q is formed. The write timing in the data write operation is determined by the control signals *CAS and *WE. Generally, when both signals *CAS and *WE are at the low level of the active state, the external write data is captured, and the internal write data is produced and transferred to internal data lines DB and /DB.
As shown in FIG. 2, the dynamic memory cell includes one MOS transistor and one capacitor. The MOS transistor allows the passage of a voltage Vg-Vth which is less than its gate voltage Vg by a threshold voltage Vth. When the potential of word line WL is at supply voltage VCC level, the signal at a VCC-Vth level is transferred to the memory cell capacitor, even if the potential of the bit line is at the high level of supply voltage VCC level.
In the word line selecting operation, the signal charges accumulated in the memory cell capacitor are transferred to the corresponding bit line. Precharge potential VBL is generally VCC/2. The low level of the bit line is the ground potential level. Therefore, the high level and the low level of the read voltage on the bit line (i.e., the voltage appearing on the bit line before the operation of the sense amplifier) become asymmetric with respect to the precharge voltage, resulting in a poor operating margin of the sense amplifier.
For this reason, the potential of the selected word line is boosted up to or above VCC+Vth in order to store the signal at the VCC level in the memory cell capacitor without a loss. This enables the high level data to be stored in the memory cell capacitor without a signal loss. Thereby, the read voltage at the high level having a sufficient value can be obtained, and the read voltage at the high level and the read voltage at the low level can be symmetric with respect to the precharge potential, so that the sense amplifier can reliably carries out the sense operation without malfunction.
Due to the boosting of word line drive signal RX to or above VCC, the rising speed of the word line potential increases, and thus the memory cell data can be read to the bit line at a high speed. Thereby, the timing for activating the sense amplifier can be set earlier, and thus the access time can be reduced.
In order to boost up word line drive signal RX, a word line drive signal generating circuit, e.g., as shown in FIG. 3 is used. The boosting circuit in the word line drive signal generating circuit applies a delay signal of the word line drive signal to one of the electrodes of a capacitor 613, so that the potential of the other electrode of capacitor 613 is boosted up through the capacitance-coupling, and thus the high level of word line drive signal RX is boosted up to the level equal to or above operating power supply voltage VCC.
In the construction shown in FIG. 3, the potential level of word line drive signal RX is always boosted up to or above operating power supply voltage VCC, while external row address strobe signal *RAS is in the low level and the semiconductor memory device is in the memory cycle. As the dynamic type semiconductor memory device is integrated to a higher degree, elements thereof have smaller sizes. In this case, the reliability of the word line becomes a matter of concern. If the thickness of the gate insulating film under the word line decreases in accordance with the miniaturization of the elements, and a high voltage is applied to the word line, the gate insulating film is likely to cause a dielectric breakdown. The miniaturization of the elements also reduces the line width of the word line, and thus the word line itself may be destructed due to electron migration, stress migration or the like caused by this high voltage.
In some operation modes such as a page mode and a static column mode of the semiconductor memory device, external row address strobe signal *RAS stays in the active state for an extremely long cycle time period. In such a long tRAS (a time period for which signal RAS is in the active state) period, in which the operation cycle of the device is extremely long, the voltage at the boosted level is continuously applied to the word line during this long cycle period. If the boosted voltage is applied to the word line for a long time period, the breakdown voltage of the word line is likely to be reduced, resulting in low reliability of the word line.